Semiconductor integrated circuit device and method for fabricating the same

ABSTRACT

A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a semiconductor integrated circuitdevice improving resistance to destruction caused by electrostaticdischarge (ESD) between a digital circuit and an analog circuit in asemiconductor integrated circuit composed of multiple power supplies.

(b) Description of the Related Art

In recent years, semiconductor integrated circuits have been developedto integrate a digital circuit and an analog circuit on a singlesemiconductor chip as LSI chip technology progresses. In this kind ofLSI chip in which the digital circuit and the analog circuit arecombined, the influence of noises given by the digital circuit to theanalog circuit is reduced by externally supplying plural power sourcesto each circuit. In order to avoid the destruction caused by ESD of theLSI chip, instead of complete separation between a power supply for thedigital circuit and a power supply for the analog circuit and between aground for the digital circuit and a ground for the analog circuit, thesemiconductor integrated circuits are constructed so as to connect thedigital circuit to the analog circuit via a circuit (hereinafter,referred to as a “protection circuit”) for avoiding destruction causedby ESD.

FIG. 11 is a diagram showing an exemplary structure of a knownsemiconductor integrated circuit 1000.

The semiconductor integrated circuit 1000 shown in FIG. 11 includes adigital circuit 1010 and an analog circuit 1050. The digital circuit1010 and the analog circuit 1050 are connected via a control signal line1080 to each other.

The digital circuit 1010 receives electrical signals from pads 1020 aand 1020 b through protection circuits 1022 a and 1022 b. A power supplypad 1024 supplies a digital power source 1034 to the protection circuits1022 a and 1022 b. A power supply pad 1025 supplies a digital groundsource 1035 to the protection circuits 1022 a and 1022 b.

Likewise, the analog circuit 1050 receives electrical signals from pads1060 a and 1060 b through the protection circuits 1062 a and 1062 b. Apower supply pad 1064 supplies an analog power source 1074 to theprotection circuits 1062 a and 1062 b. A power supply pad 1065 suppliesan analog ground source 1075 to the protection circuits 1062 a and 1062b.

FIG. 12 is a diagram showing an exemplary structure of the protectioncircuits 1022 a, 1022 b, 1062 a, and 1062 b. For example, as shown inFIG. 12, each circuit is constructed using diodes so as to absorb asurge voltage. Thereby, even when surge voltages are mixed between thepower supply pad 1024 for supplying a power source to the digitalcircuit 1010 and each of the pads 1020 a and 1020 b for inputtingelectrical signals, between the power supply pad 1025 and each of pads1020 a and 1020 b, between the power supply pad 1064 for likewisesupplying a power source to the analog circuit 1050 and each of the pads1060 a and 1060 b for inputting electrical signals, and further betweenthe power supply pad 1065 and each of the pads 1060 a and 1060 b,respectively, charges are bypassed by the circuit shown in FIG. 12,thereby avoiding destruction caused by ESD of the digital circuit 1010and the analog circuit 1050.

As described above, the protection circuits 1022 a and 1022 b and theprotection circuits 1062 a and 1062 b function only for thecorresponding digital circuit 1010 and analog circuit 1050. Inconsideration of the case where charges are bypassed by the respectiveprotection circuits 1022 a, 1022 b, 1062 a, and 1062 b, leading to thedestruction caused by ESD between the digital circuit 1010 and theanalog circuit 1050, a protection circuit 1090 is connected between thedigital circuit 1010 and the analog circuit 1050. That is, a powersource 1034 for the digital circuit 1010 and a power source 1074 for theanalog circuit 1050 are connected via the protection circuit 1090 toeach other, and ground sources 1035 and 1075 are done likewise.

FIG. 13 is a diagram showing an exemplary structure of the protectioncircuit 1090. For example, as shown in FIG. 13, the circuit isconstructed using diodes so as to prevent the destruction caused by ESDfrom being caused between the digital circuit 1010 and the analogcircuit 1050. The protection circuit 1090 prevents the digital circuit1010 and the analog circuit 1050 from being directly connected to eachother so that it also has the function of absorbing noises from thedigital circuit 1010 to the analog circuit 1050.

Many protection circuits other than those having the structures shown inFIGS. 12 and 13 have been devised (for example, see Japanese UnexaminedPatent Publications No. 10-56138 and 11-27404).

FIG. 14 is a diagram showing an example of a connection relationshipbetween the pad in the semiconductor integrated circuit 1000 shown inFIG. 11 and a terminal of a package substrate.

For example, the pad 1025 in the semiconductor integrated circuit 1000is electrically connected via a lead 1327 to a terminal 1326 located ona package substrate 1300 shown in FIG. 14. The connections of the otherpads are also performed likewise.

FIG. 15 is a diagram showing an example of connection relationshipsbetween the terminals of the package substrate 1300 and external pins.As shown in FIG. 15, the terminal 1326 is electrically connected via aninterconnect 1427 to an external pin 1426 inside the package substrate1300. The connections of the other terminals are also performedlikewise.

In this way, the package substrate 1300 and the semiconductor integratedcircuit 1000 are connected to each other, and thereafter they arepackaged by resin 1410 or the like so as to form an LSI chip 1400.

FIG. 16 is a flow chart showing process steps for fabricating the LSIchip 1400.

As shown in FIG. 16, the semiconductor integrated circuit 1000 isdesigned in step ST2000, and thereafter the process proceeds to stepST2010 to fabricate the semiconductor integrated circuit 1000. Next, theprocess proceeds to step ST2020 to integrate the semiconductorintegrated circuit 1000 and the package circuit 1300, thereby formingthe LSI chip 1400.

Thereafter, the process proceeds to step ST2100 for carrying out an LSItest for the LSI chip 1400. That is, step ST2100 for carrying out theLSI test includes at least step ST2110 for testing whether or not thedigital circuit 1010 and the analog circuit 1050 satisfy thespecification and step ST2120 for testing these circuits for destructioncaused by ESD. After the LSI test in step ST2100, if it is found thatthe digital circuit 1010 and the analog circuit 1050 satisfy thespecification and no destruction caused by ESD occurs, then it followsthat the LSI chip 1400 has been completed. On the other hand, if it isfound that the digital circuit 1010 or the analog circuit 1050 does notsatisfy the specification or that the destruction caused by ESD occursin the digital circuit 1010 or the analog circuit 1050, the processreturns to the step ST2000 and repeats the subsequent steps.

However, as described above, the protection circuit 1090 is inserted forthe purpose of reducing the influence of noises produced in the digitalcircuit 1010 and improving resistance to the ESD. However, when theperiod during which surge charges pass through the protection circuit1090 is long, surge voltages may not be appropriately discharged. Atthis time, a high voltage may be applied, via a control signal thatflows into a control signal line 1080 connecting the digital circuit1010 to the analog circuit 1050, to these circuits, and thus a portionof the digital circuit 1010 or the analog circuit 1050 connecting thecontrol signal line 1080 therebetween may be destroyed.

Such a case can be handled by changing the protection circuit 1090 inits design so as to reduce the period during which the surge chargespass through the protection circuit 1090. More particularly, it can behandled by again carrying out step ST2000 shown in FIG. 16. However, thesemiconductor integrated circuit 1000 need again be fabricated as shownin step ST2010 shown in FIG. 16. The semiconductor integrated circuit1000 is fabricated through multiple fabrication process steps.Therefore, a long period exceeding at least one month becomes necessaryfor again fabricating the semiconductor integrated circuit 1000. Inaddition, a mask required for fabrication costs very expensive. Besides,finally, the resistance to surge voltages applied to the LSI chip 1400and the influence of noises need totally be judged. It is difficult tochange the design of the protection circuit 1090 in view of all theconditions at the change of the design. Therefore, at the change of thedesign, it cannot surely be judged that the resistance to the ESD isimproved and the influence of noises is also small.

This kind of destruction caused by ESD occurs with a high frequency inthe process of carrying the LSI chip or the process of mounting the LSIchip to the substrate.

SUMMARY OF THE INVENTION

A first object of the present invention is to provide a semiconductorintegrated circuit capable of improving resistance to ESD at a low costin a short period. A second object of the present invention is toprovide a method for fabricating a semiconductor integrated circuitdevice capable of improving resistance to ESD at a low cost in a shortperiod.

In order to solve the problem, a first semiconductor integrated circuitdevice of the present invention including a digital circuit and ananalog circuit which are integrated on a single semiconductor chip,comprises: a first electrostatic destruction protection circuit,connected to the digital circuit, for protecting the digital circuitfrom destruction caused by ESD in the digital circuit by an influence ofan input digital signal; and a second electrostatic destructionprotection circuit, connected to the analog circuit, for protecting theanalog circuit from destruction caused by ESD in the analog circuit byan influence of an input analog signal, wherein a first groundingconductor connected to the first electrostatic destruction protectioncircuit and a second grounding conductor connected to the secondelectrostatic destruction protection circuit are connected to each otheroutside the semiconductor integrated circuit device.

According to the first semiconductor integrated circuit device, thefirst grounding conductor connected to the first electrostaticdestruction protection circuit and the second grounding conductorconnected to the second electrostatic destruction protection circuit areconnected to each other outside the semiconductor integrated circuitdevice. Therefore, a semiconductor integrated circuit device capable ofimproving resistance to ESD can be provided at a low cost in a shortperiod.

In the first semiconductor integrated circuit device of the presentinvention, the first grounding conductor and the second groundingconductor are preferably connected to each other inside a packagesubstrate of the semiconductor integrated circuit device.

Thus, a semiconductor integrated circuit device capable of improvingresistance to ESD can be provided at a low cost in a short period.

In the first semiconductor integrated circuit device of the presentinvention, the first grounding conductor and the second groundingconductor are preferably connected to each other outside a packagesubstrate of the semiconductor integrated circuit device.

Thus, whether or not the first grounding conductor and the secondgrounding conductor are to be connected to each other can be easilyselected, and a trade-off between the enhancement of resistance todestruction caused by ESD and reduction of noises can be made.

In the first semiconductor integrated circuit device of the presentinvention, it is preferable that the first grounding conductor and thesecond grounding conductor are connected to each other using acapacitance outside a package substrate of the semiconductor integratedcircuit device.

Thus, the capacitance can be arbitrarily set. Therefore, a trade-offbetween the enhancement of resistance to destruction caused by ESD andreduction of noises can be made in more detail.

In the first semiconductor integrated circuit device of the presentinvention, the first grounding conductor and the second groundingconductor are preferably connected to each other via a member forelectrically connecting the semiconductor integrated circuit device to apackage substrate of the semiconductor integrated circuit device.

Thus, resistance to destruction caused by ESD can be enhanced withoutchanging the package substrate itself.

A first method for fabricating a semiconductor integrated circuit deviceincluding a digital circuit and an analog circuit are integrated on asingle semiconductor chip, comprises: a circuit test step of judgingwhether or not the digital circuit connected to a first electrostaticdestruction protection circuit for protecting the digital circuit fromdestruction caused by ESD in the digital circuit by an influence of aninput digital signal and the analog circuit connected to a secondelectrostatic destruction protection circuit for protecting the analogcircuit from destruction caused by ESD in the analog circuit by aninfluence of an input analog signal satisfy the specification; anelectrostatic destruction test step of, when it is judged in the circuittest step that both the digital circuit and the analog circuit satisfythe specification, judging whether or not destruction caused by ESDoccurs for the digital circuit and the analog circuit; and an externalconnection step of, when it is judged in the electrostatic destructiontest step that destruction caused by ESD occurs in at least one of thedigital circuit and the analog circuit, connecting a first groundingconductor connected to the first electrostatic destruction protectioncircuit to a second grounding conductor connected to the secondelectrostatic destruction protection circuit outside the semiconductorintegrated circuit device.

According to the first method for fabricating a semiconductor integratedcircuit device of the present invention, the first grounding conductorand the second grounding conductor are connected to each other outsidethe semiconductor integrated circuit device in accordance with resultsof the first and second LSI test steps. Therefore, a method forfabricating a semiconductor integrated circuit device capable ofimproving resistance to ESD can be provided at a low cost in a shortperiod.

In the first method for fabricating a semiconductor integrated circuitdevice of the present invention, the external connection step ispreferably the step of connecting the first grounding conductor to thesecond grounding conductor inside a package substrate of thesemiconductor integrated circuit device.

Thus, a method for fabricating a semiconductor integrated circuit devicecapable of improving resistance to ESD can be provided at a low cost ina short period.

In the first method for fabricating a semiconductor integrated circuitdevice of the present invention, the external connection step ispreferably the step of connecting the first grounding conductor to thesecond grounding conductor outside a package substrate of thesemiconductor integrated circuit device.

Thus, whether or not the first grounding conductor and the secondgrounding conductor are to be connected to each other can be easilyselected, and a trade-off between the enhancement of resistance todestruction caused by ESD and reduction of noises can be made.

In the first method for fabricating a semiconductor integrated circuitdevice of the present invention, the external connection step ispreferably the step of connecting the first grounding conductor to thesecond grounding conductor using a capacitance outside a packagesubstrate of the semiconductor integrated circuit device.

Thus, the capacitance can be arbitrarily set. Therefore, a trade-offbetween the enhancement of resistance to destruction caused by ESD andreduction of noises can be made in more detail.

In the first method for fabricating a semiconductor integrated circuitdevice of the present invention, the external connection step ispreferably the step of connecting the first grounding conductor to thesecond grounding conductor via a member for electrically connecting thesemiconductor integrated circuit device to a package substrate of thesemiconductor integrated circuit device.

Thus, resistance to destruction caused by ESD can be enhanced withoutchanging the package substrate itself.

A second method for fabricating a semiconductor integrated circuitdevice comprises: a first package production step of producing a firstpackage substrate in which a first grounding conductor connected to afirst electrostatic destruction protection circuit for protecting afirst digital circuit from destruction caused by ESD in the firstdigital circuit by an influence of an input digital signal and a secondgrounding conductor connected to a second electrostatic destructionprotection circuit for protecting a first analog circuit fromdestruction caused by ESD in the first analog circuit by an influence ofan input analog signal are not connected to each other inside a packagesubstrate of a first semiconductor integrated circuit device includingthe first digital circuit and the first analog circuit which areintegrated on a single semiconductor chip; a second package productionstep of producing a second package substrate in which a third groundingconductor connected to a third electrostatic destruction protectioncircuit for protecting a second digital circuit from destruction causedby ESD in the second digital circuit by an influence of an input digitalsignal and a fourth grounding conductor connected to a fourthelectrostatic destruction protection circuit for protecting a secondanalog circuit from destruction caused by ESD in the second analogcircuit by an influence of an input analog signal are connected to eachother inside a package substrate of a second semiconductor integratedcircuit device including the second digital circuit and the secondanalog circuit which are integrated on a single semiconductor chip; afirst LSI test step to be performed after the first package productionstep, including a first circuit test step of judging whether or not thefirst digital circuit and the first analog circuit satisfy thespecification and a first electrostatic destruction test step of, whenit is judged in the first circuit test step that both the first digitalcircuit and the first analog circuit satisfy the specification, judgingwhether or not destruction caused by ESD occurs for the first digitalcircuit and the first analog circuit; a second LSI test step to beperformed after the second package production step, including a secondcircuit test step of judging whether or not the second digital circuitand the second analog circuit satisfy the specification and a secondelectrostatic destruction test step of, when it is judged in the secondcircuit test step that both the second digital circuit and the secondanalog circuit satisfy the specification, judging whether or notdestruction caused by ESD occurs for the second digital circuit and thesecond analog circuit; a first package selection step of, when it isjudged in the first electrostatic destruction test step of the first LSItest step that no destruction caused by ESD occurs in both the firstdigital circuit and the first analog circuit, selecting the firstpackage substrate; and a second package selection step of, when it isjudged in the first electrostatic destruction test step of the first LSItest step that destruction caused by ESD occurs in at least one of thefirst digital circuit and the first analog circuit and it is judged inthe second electrostatic destruction test step of the second LSI teststep that no destruction caused by ESD occurs in both the second digitalcircuit and the second analog circuit, selecting the second packagesubstrate.

According to the second method for fabricating a semiconductorintegrated circuit device of the present invention, a period requiredfor LSI test can be reduced, and a method for fabricating asemiconductor integrated circuit device capable of improving resistanceto ESD can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explaining a semiconductor integrated circuitaccording to an embodiment of the present invention.

FIG. 2 is a view showing an LSI chip for explaining an example in whichconnection is performed inside a package substrate.

FIG. 3 is a view schematically showing a certain one of plural layers inthe package substrate.

FIG. 4 is a view showing the LSI chip for explaining an example in whichconnection is performed outside the package substrate.

FIG. 5 is a view showing the back surface of the LSI chip.

FIG. 6 is a view showing the LSI chip for explaining an example in whichconnection is performed using a capacitance outside the packagesubstrate.

FIG. 7 is a view showing the back surface of the package substrate.

FIG. 8 is a diagram showing the LSI chip for explaining an example inwhich connection is performed using a lead outside.

FIG. 9 is a flow chart for explaining a method for fabricating asemiconductor integrated circuit device according to a modified exampleof this embodiment.

FIG. 10 is a flow chart for explaining another method for fabricating asemiconductor integrated circuit device.

FIG. 11 is a diagram showing an exemplary structure of a knownsemiconductor integrated circuit.

FIG. 12 is a diagram showing an example of a protection circuit.

FIG. 13 is a diagram showing an example of another protection circuit.

FIG. 14 is a view for explaining connection relationships between padsin the semiconductor integrated circuit and terminals of the packagesubstrate.

FIG. 15 is a view for explaining connection relationships between theterminals of the package substrate and external pins.

FIG. 16 is a flow chart for explaining a known method for fabricating anLSI chip.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will be described hereinafterwith reference to the drawings.

FIG. 1 is a diagram for explaining a semiconductor integrated circuit1000 according to an embodiment of the present invention.

The semiconductor integrated circuit 1000 shown in FIG. 1 includes adigital circuit 1010 and an analog circuit 1050. The digital circuit1010 and the analog circuit 1050 are connected via a control signal line1080 to each other.

The digital circuit 1010 receives electrical signals from pads 1020 aand 1020 b through protection circuits 1022 a and 1022 b (bothcorresponding to a first electrostatic destruction protection circuit).A power supply pad 1024 supplies a digital power source 1034 to theprotection circuits 1022 a and 1022 b. A power supply pad 1025 suppliesa digital ground source 1035 to the protection circuits 1022 a and 1022b.

Likewise, the analog circuit 1050 receives electrical signals from pads1060 a and 1060 b through protection circuits 1062 a and 1062 b (bothcorresponding to a second electrostatic destruction protection circuit).A power supply pad 1064 supplies an analog power source 1074 to theprotection circuits 1062 a and 1062 b. A power supply pad 1065 suppliesan analog ground source 1075 to the protection circuits 1062 a and 1062b.

The semiconductor integrated circuit 1000 shown in FIG. 1 is distinctfrom the known semiconductor integrated circuit 1000 shown in FIG. 11 inthat an interconnect (corresponding to a first grounding conductor) towhich the digital ground source 1035 is supplied and an interconnect(corresponding to a second grounding conductor) to which the analogground source 1075 is supplied are electrically connected via the powersupply pad 1025 and the power supply pad 1065 to each other by using aconductor 100 outside the semiconductor integrated circuit 1000.Thereby, a period during which surge charges pass through the protectioncircuit 1090 can be reduced, and static electricity can be appropriatelydischarged.

In this case, since the interconnect to which the digital ground source1035 is supplied and the interconnect to which the analog ground source1075 is supplied are connected to each other, it is feared that noisesproduced in the digital circuit 1010 enter the analog circuit. However,an interconnect capacitance outside the semiconductor integrated circuit1000 is approximately 1000 times as large as that inside thesemiconductor integrated circuit 1000. Therefore, the noises produced inthe digital circuit 1010 hardly affect the analog circuit 1050.

Hereinafter, a description will be given of examples in which aninterconnect to which a digital ground source 1035 is supplied and aninterconnect to which an analog ground source 1075 is supplied areconnected to each other outside the semiconductor integrated circuit1000.

EXAMPLE OF CONNECTION (1)

FIG. 2 is a view showing an LSI chip 200 for explaining an example inwhich the connection is performed inside a package substrate 210.

The LSI chip 200 shown in FIG. 2 comprises the semiconductor integratedcircuit 1000, the package substrate 210 and an encapsulating compound212. A terminal 226 and a terminal 266 are ones constructed on thepackage substrate 210. The terminal 226 is connected to a power supplypad 1025 in the semiconductor integrated circuit 1000, that is, theinterconnect to which a digital ground source 1035 is supplied. Theterminal 266 is connected to a power supply pad 1065 in thesemiconductor integrated circuit 1000, that is, the interconnect towhich an analog ground source 1075 is supplied. The terminals 226 and266 are connected via interconnects 227 and 267 to external pins 228 and268 of the LSI chip 200, respectively.

The power supply pad 1025 for supplying the digital ground source 1035and the power supply pad 1065 for supplying the analog ground source1075 are connected to each other by connecting the interconnects 227 and267 via an interconnect 280 to each other inside the package substrate210.

A description will be given of the case where the package substrate 210is composed of multiple layers.

FIG. 3 is a view schematically showing a certain one of plural substratelayers in the package substrate 210. More particularly, FIG. 3 is a viewtaken along the cross sections L1 and L2 shown in FIG. 2. As shown inFIG. 3, the interconnects 227 and 267 are connected via the interconnect280 to each other in the layer 310 in which these interconnects 227 and267 are formed. In order to facilitate the understanding, FIG. 3 issimplified by showing interconnect layers and the like rectilinearly.However, it is needless to say that the connection is specificallyperformed in a convenient position for an interconnect pattern in viewof various elements.

EXAMPLE OF CONNECTION (2)

FIG. 4 is a view showing an LSI chip 400 for explaining an example inwhich the connection is performed outside the package substrate 410.

The LSI chip 400 shown in FIG. 4 comprises the semiconductor integratedcircuit 1000, the package substrate 410, and an encapsulating compound212. From an interconnect 427 connected to the interconnect of thesemiconductor integrated circuit 1000 to which the digital ground source1035 is supplied and an interconnect 467 connected to the interconnectthereof to which the analog ground source 1075 is supplied, theiroutputs are led out of the package substrate 410 and are connected viaan interconnect 480 to each other on the back surface of the LSI chip400.

FIG. 5 is a view showing the back surface of the LSI chip 400. Morespecifically, a connection part of the interconnect 427 and a connectionpart of the interconnect 467 are electrically connected via theinterconnect 480 to each other.

Thereby, whether or not the connection using the interconnect 480 is tobe performed can be selected outside. Therefore, after completion of theLSI chip 400, a trade-off between the enhancement of resistance topressure caused by ESD and reduction of noises can be made.

EXAMPLE OF CONNECTION (3)

FIG. 6 is a view showing the LSI chip 400 for explaining an example inwhich the connection is performed using a capacitance outside thepackage substrate 410.

According to the LSI chip 400 shown in FIG. 6, from the interconnect 427connected to the interconnect to which the ground source 1035 issupplied and the interconnect 467 connected to the interconnect to whichthe ground source 1075 is supplied, their outputs are led out of thepackage substrate 410 and are connected to each other on the backsurface of the LSI chip 400, as in the case of the LSI chip 400 shown inFIG. 4. However, the one shown in FIG. 6 is distinct from the one shownin FIG. 4 in that the interconnects 427 and 467 are connected to eachother by using not the interconnect 480 but a condenser 680.

FIG. 7 is a view showing the back surface of the package substrate 400.More particularly, a connection part of the interconnect 427 and aconnection part of the interconnect 467 are connected to each other byusing the condenser 680.

Thereby, the capacitance of the condenser can be arbitrarily selectedoutside at the connection using the condenser 680. Therefore, aftercompletion of the LSI chip 400, a trade-off between the enhancement ofresistance to pressure caused by ESD and reduction of noises can beadjusted more finely.

EXAMPLE OF CONNECTION (4)

FIG. 8 is a view showing the LSI chip 400 for explaining an example inwhich the connection is performed outside by using a lead.

The power supply pad 1025 connected to the interconnect of thesemiconductor integrated circuit 1000 to which the digital ground source1035 is supplied and the power supply pad 1065 connected to theinterconnect thereof to which the analog ground source 1075 is suppliedare connected to each other by connecting a terminal 1326 located on apackage substrate 1300 and the power supply pad 1065 via a lead 880 toeach other. Although in this embodiment a description is given of thecase where the terminal 1326 and the power supply pad 1065 are connectedvia the lead to each other, it is needless to say that a terminal 1366and the power supply pad 1025 may also be connected via the lead to eachother. It is desirable in each case that the distance at which they areconnected via a lead be short.

Thereby, resistance to pressure caused by ESD can be enhanced withoutchanging the package substrate as shown in FIGS. 2 and 3.

Hereinafter, methods for fabricating the semiconductor integratedcircuit device will be described as modified examples of thisembodiment.

METHOD FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE (1)

FIG. 9 is a flow chart for explaining a method for fabricating asemiconductor integrated circuit device according to a modified exampleof this embodiment of the present invention.

First, a semiconductor integrated circuit 1000 is designed in stepST2000, and thereafter the process proceeds to step ST2010 to fabricatethe semiconductor integrated circuit 1000. Next, in step ST2020, thesemiconductor integrated circuit 1000 and a package substrate 1300 areintegrated, for example, to form an LSI chip 1400 shown in FIG. 14. Theprocess proceeds to step ST2100 for carrying out an LSI test.

Step ST2100 for carrying out the LSI test includes at least step ST2110(corresponding to a circuit test step) for testing operations of thedigital circuit 1010 and the analog circuit 1050 and step ST2120(corresponding to an electrostatic destruction test step) for testingthese circuits for destruction caused by ESD.

In step ST2110 for testing the operations of the digital circuit 1010and the analog circuit 1050, whether or not the operations are performedas specified is judged. When the operations are performed as specified(if YES in step ST2110), the process proceeds to step ST2120. When theoperations are not performed as specified (if NO in step ST2110), theprocess returns to step ST2000 so as to again begin with a design of asemiconductor integrated circuit.

Next, step ST2120 for testing the circuits for destruction caused by ESDis carried out, for example, in the following manner.

First, for example, external pins 1426 and 1466 shown in FIG. 15 arefixed to a grounding level (potential 0), and a high voltage is appliedsequentially to the other external pins. When the operation of thevoltage-applied LSI chip 1400 is checked and consequently a normaloperation is performed, it is judged that no destruction caused by ESDtakes place (YES in step ST2120). On the other hand, when a normaloperation is not performed, that is, when destruction caused by ESDtakes place (if NO in step ST2120), the process proceeds to step ST2200.

In step ST2200, the power supply pad 1025 for supplying the digitalground source 1035 and the power supply pad 1065 for supplying theanalog ground source 1075 are electrically connected to each otheroutside the semiconductor integrated circuit 1000 (corresponding to anexternal connection step). This connecting manner is as described above.

Thereafter, the process returns to step ST2020, wherein thesemiconductor integrated circuit 1000 having the process of the stepST2200 completed and the package substrate are integrated. Subsequently,the LSI test of step ST2100 is carried out. Then, if it becomes possibleto judge that the digital circuit 1010 and the analog circuit 1050satisfy the specification and no destruction caused by ESD takes place,this means that the semiconductor integrated circuit device iscompleted.

As obvious from the above description, even when destruction caused byESD takes place in step ST2120, steps for the design and fabrication ofthe semiconductor integrated circuit 1000 (steps ST2000 and ST2010) canbe omitted. Therefore, the LSI chip 1400 can be completed in a shortperiod.

METHOD FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE (2)

Next, another method for fabricating a semiconductor integrated circuitdevice will be described.

FIG. 10 is a flow chart for explaining another method for fabricating asemiconductor integrated circuit device.

In the fabricating method shown in FIG. 10, first, operations in stepsST2000 and ST2010 are performed as in FIG. 9. In this fabricatingmethod, the process proceeds to step ST2400.

Step ST2400 includes a first package production step (step ST2020) and asecond package production step (steps ST2205 and ST2025).

The first package production step (step ST2020) is one for integratingthe semiconductor integrated circuit 1000 in which an interconnect towhich the ground source 1035 is supplied (here, corresponding to a firstgrounding conductor) and an interconnect to which a ground source 1075is supplied (here, corresponding to a second grounding conductor) arenot connected to each other and the package substrate.

In the second package production step (steps ST2205 and ST2025), first,an interconnect to which the digital ground source 1035 is supplied(here, corresponding to a third grounding conductor) and an interconnectto which the analog ground source 1075 is supplied (here, correspondingto a fourth grounding conductor) are electrically connected via thepower supply pads 1025 and 1065 for supplying the ground sources 1035and 1075, respectively, to each other outside the semiconductorintegrated circuit (step ST2205). Then, the process proceeds to a step(step ST2205) for integrating the semiconductor integrated circuit 1000in which these interconnects are electrically connected to each otheroutside as described above and the package substrate. This connectingmanner is as described above.

To be specific, in step ST2020 of step ST2400, the semiconductorintegrated circuit 1000 in which the interconnect to which the groundsource 1035 is supplied and the interconnect to which the ground source1075 is supplied are not electrically connected to each other outsideand the package substrate are integrated. In addition, in step ST2025 ofstep ST2400, the semiconductor integrated circuit 1000 in which theinterconnect to which the ground source 1035 is supplied and theinterconnect to which the ground source 1075 is supplied areelectrically connected to each other outside and the package substrateare integrated. Thereafter, the process proceeds to step ST2500.

In step ST2500, a first LSI test step (step ST2100) and a second LSItest step (step ST2105) are carried out, so that the subsequent step isdetermined. In steps ST2100 and ST2105, the LSI test is carried out asdescribed above.

More specifically, first, when the first LSI test in step ST2100 of stepST2500 judges that the LSI is “normal” (that is, when the test of thedigital circuit 1010 (here corresponding to a first digital circuit) andthe analog circuit 1050 (here corresponding to a first analog circuit),the test here corresponding to a first circuit test step, and the testof the circuits for destruction caused by ESD, here corresponding to afirst electrostatic destruction test step, both judge that they are“normal”), the process proceeds to step ST2301 regardless of the resultof the second LSI test in step ST2105. In step ST2301, a packagesubstrate on which the power supply pad 1025 for supplying the digitalground source 1035 and the power supply pad 1065 for supplying theanalog ground source 1075 are not electrically connected to each otheroutside the semiconductor integrated circuit 1000 is selected(corresponding to a first package selection step).

When the first LSI test in step ST2100 judges that the LSI is “notnormal” (that is, the test of the digital circuit 1010 and the analogcircuit 1050 judges that they are “normal” and the test of the circuitsfor the destruction caused by ESD judges that they are “not normal”) butthe second LSI test in step ST2105 judges that the LSI is “normal” (thatis, the test of the digital circuit 1010 (here corresponding to a seconddigital circuit) and the analog circuit 1050 (here corresponding to asecond analog circuit), the test here corresponding to a second circuittest step, and the test of the circuits for the destruction caused byESD, here corresponding to a second electrostatic destruction test step,both judge that they are “normal”), the process proceeds to step ST2302.In step ST2302, a package substrate on which the power supply pad 1025for supplying the digital ground source 1035 and the power supply pad1065 for supplying the analog ground source 1075 are electricallyconnected to each other outside the semiconductor integrated circuit1000 is selected (corresponding to a second package selection step).

When the results of the first and second LSI tests in steps ST2100 andST2105 of step ST2500 are other than the above results (that is, whenthe circuits are judged as “not normal” in the first or second circuittest step and when the circuits are judged as “normal” in the firstcircuit test step but judged as “not normal” in the first electrostaticdestruction test step and then the circuits are judged as “normal” inthe second circuit test step but judged as “not normal” in the secondelectrostatic destruction test step), the process returns to step ST2000to again begin with the design of the semiconductor integrated circuit1000.

As described above, according to the method for fabricating asemiconductor integrated circuit device shown in FIG. 10, a periodrequired for a further LSI test (step ST2100) to be performed after stepST2200 shown in FIG. 9 can be reduced as compared with the fabricatingmethod shown in FIG. 9.

Although in the above examples the cases where the interconnect to whichthe digital ground source 1035 is supplied and the interconnect to whichthe analog ground source 1075 is supplied are connected to each otherinside or outside the package substrate, or by further using the leadare described with reference to FIGS. 2 to 8, it is needless to say thatthe shapes of the connection parts, the terminals and the pads are notrestricted to those shown in the drawings. Physical positions of pads orthe like are not restricted to those in this embodiment.

Although the case where the external terminal of the LSI chip is locatedon the back surface of the package substrate is described, the casewhere it is located on the side thereof is likewise applicable to thisinvention. Although the case where the connection is performed on theback surface thereof by using the interconnect or the condenser isdescribed with reference to FIGS. 3 and 5, the case where the connectionis performed on the side thereof is likewise applicable to thisinvention. In the case of FIG. 3 or 5, it is not impossible that theconnection is likewise performed on the front surface thereof.

1-6. (canceled)
 7. The method for fabricating a semiconductor integratedcircuit device of claim 6, wherein the external connection step is thestep of connecting the first grounding conductor to the second groundingconductor inside a package substrate of the semiconductor integratedcircuit device.
 8. The method for fabricating a semiconductor integratedcircuit device of claim 6, wherein the external connection step is thestep of connecting the first grounding conductor to the second groundingconductor outside a package substrate of the semiconductor integratedcircuit device.
 9. The method for fabricating a semiconductor integratedcircuit device of claim 6, wherein the external connection step is thestep of connecting the first grounding conductor to the second groundingconductor using a capacitance outside a package substrate of thesemiconductor integrated circuit device.
 10. The method for fabricatinga semiconductor integrated circuit device of claim 6, wherein theexternal connection step is the step of connecting the first groundingconductor to the second grounding conductor via a member forelectrically connecting the semiconductor integrated circuit device to apackage substrate of the semiconductor integrated circuit device.
 11. Amethod for fabricating a semiconductor integrated circuit device,comprising: a first package production step of producing a first packagesubstrate in which a first grounding conductor connected to a firstelectrostatic destruction protection circuit for protecting a firstdigital circuit from destruction caused by ESD in the first digitalcircuit by an influence of an input digital signal and a secondgrounding conductor connected to a second electrostatic destructionprotection circuit for protecting a first analog circuit fromdestruction caused by ESD in the first analog circuit by an influence ofan input analog signal are not connected to each other inside a packagesubstrate of a first semiconductor integrated circuit device includingthe first digital circuit and the first analog circuit which areintegrated on a single semiconductor chip; a second package productionstep of producing a second package substrate in which a third groundingconductor connected to a third electrostatic destruction protectioncircuit for protecting a second digital circuit from destruction causedby ESD in the second digital circuit by an influence of an input digitalsignal and a fourth grounding conductor connected to a fourthelectrostatic destruction protection circuit for protecting a secondanalog circuit from destruction caused by ESD in the second analogcircuit by an influence of an input analog signal are connected to eachother inside a package substrate of a second semiconductor integratedcircuit device including the second digital circuit and the secondanalog circuit which are integrated on a single semiconductor chip; afirst LSI test step to be performed after the first package productionstep, including a first circuit test step of judging whether or not thefirst digital circuit and the first analog circuit satisfy thespecification and a first electrostatic destruction test step of, whenit is judged in the first circuit test step that both the first digitalcircuit and the first analog circuit satisfy the specification, judgingwhether or not destruction caused by ESD occurs for the first digitalcircuit and the first analog circuit; a second LSI test step to beperformed after the second package production step, including a secondcircuit test step of judging whether or not the second digital circuitand the second analog circuit satisfy the specification and a secondelectrostatic destruction test step of, when it is judged in the secondcircuit test step that both the second digital circuit and the secondanalog circuit satisfy the specification, judging whether or notdestruction caused by ESD occurs for the second digital circuit and thesecond analog circuit; a first package selection step of, when it isjudged in the first electrostatic destruction test step of the first LSItest step that no destruction caused by ESD occurs in both the firstdigital circuit and the first analog circuit, selecting the firstpackage substrate; and a second package selection step of, when it isjudged in the first electrostatic destruction test step of the first LSItest step that destruction caused by ESD occurs in at least one of thefirst digital circuit and the first analog circuit and it is judged inthe second electrostatic destruction test step of the second LSI teststep that no destruction caused by ESD occurs in both the second digitalcircuit and the second analog circuit, selecting the second packagesubstrate.